The Staggered Model: Improving the Practicality of Pfair Scheduling

We consider the implementation of a Pfair scheduler on a symmetric multiprocessor (SMP) architecture. Although SMPs seem well-suited for Pfair scheduling, simulations presented herein suggest that bus contention resulting from the simultaneous scheduling of all processors can substantially degrade performance. To correct this problem, we propose a staggered model for Pfair scheduling under which scheduling points are uniformly distributed over time. Additional simulations are presented to demonstrate the effectiveness of the staggered model at reducing bus contention. To facilitate the use of the staggered model, we present an efficient scheduling algorithm and explain how existing Pfair results can be adapted for use under the new model. In addition to supporting the staggered model, the presented algorithm provides other practical benefits, including improved cache performance and reduced scheduling overhead. ∗Work supported by NSF grants CCR 9972211, CCR 9988327, ITR 0082866, and CCR 0204312.